The present invention relates generally to the electrical, electronic and computer arts, and, more particularly, to implementations of decision feedback equalizers for high-speed data transmission.
Modern data networks require high-speed data communication with serial link data rates of more than 10 Gbit/s. In this bandwidth range, a further increase of serial link data rates is challenging due to the limited general bandwidth. The general bandwidth is usually determined by dielectric losses and reflections on the transmission channel which result in a widening of the transmitted signal pulses over more than one unit interval, so that the received signal is distorted by intersymbol interference (ISI).
These signal distortions are usually compensated for by means of equalizing functions in the receiving circuitry, such as feed-forward equalizing and decision-feedback equalizing. A decision-feedback equalizer (DFE) is capable of reducing signal distortions while leaving noise and cross-talk unaffected.
In general, a decision-feedback equalizer is included in the data path of incoming data and is substantially configured to compensate for the effects of one transmitted pulse onto one or more succeeding pulses of the incoming data stream of digitalized data samples. The general concept of a decision-feedback equalizer implementation is to provide at least one comparator used to translate the single pulses of the stream of digitalized data samples into a bit stream. By means of the comparator, the digitalized data samples are each compared with a respective variable threshold value, which may be generated depending on the preceding (history of) data samples tapped from the output of the decision-feedback equalizer. The variable threshold value is obtained by delaying the bit outputs of the decision-feedback equalizer by one or more clock cycles in a number of delay stages, by weighting each of the delayed bit outputs of the decision-feedback equalizer after each stage by a predetermined (preset) coefficient and by then adding the results. The coefficients are adapted to a standard pulse response of the specific transmission channel.
An additional approach, known as speculation or loop-unrolling, is to precompute the variable threshold values for each pattern of delayed DFE bit outputs. Speculation or loop-unrolling for DFE is a technique that implements all possible weighted summations at the output of a finite impulse response (FIR) filter in the DFE feedback path in order to reduce the critical path time of the DFE coefficients' summation time. All possible combinations of N post-cursors (N taps) intersymbol interference terms are accordingly generated in a speculative decision-feedback equalizer of the order N, so that a total of 2N combinations or speculations are generated, where N is an integer. The correct decision is selected among the 2N speculations on the basis of the last N decisions. This approach should help to save area and power impact of the line of adding circuits. However, hardware complexity grows exponentially with the number N of taps; i.e., the number of considered historical data samples. As for each of the threshold values a separate comparator latch is needed, the outputs of which are to be selected by a multiplexer, the overall circuitry has the disadvantage of requiring a large circuit area and having high power consumption.
U.S. Pat. No. 8,121,186 B2 discloses a speculative digital DFE circuit which is operable to reduce intersymbol interference without the timing constraints exhibited by existing DFE circuits. In particular, speculative digital DFE circuit operates to pre-calculate two competing adjustment feedback values-one based on a speculation that the result from processing the succeeding bit (i.e., a decision output) will be logic “1” and the other based on a speculation that the result from processing the succeeding bit will be logic “0.” Once the result from the succeeding bit is available, the pre-calculated adjustment feedback value corresponding to the correctly speculated output value can be immediately selected to process the subsequent input bits. In this way, latency between determination of a succeeding bit and providing a data dependent input for processing a subsequent bit can be greatly reduced as the time required to perform adjustment calculations is effectively eliminated from the latency.